1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register minimizing a bias stress applied to a switching element.
2. Discussion of the Related Art
Recently, various flat-panel display devices have appeared on the market to overcome the disadvantages of a cathode ray tube (CRT), such as, weight, volume, etc. Such flat-panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), a light emitting display (LED), etc.
A conventional LCD displays images thereon as the light transmission of a liquid crystal layer is controlled using electric fields. To this end, the LCD includes an LCD panel in which liquid crystal (LC) cells are aligned in matrix form and a drive circuit for driving the LCD panel.
The LCD panel is configured such that gate lines and data lines cross. Liquid crystal (LC) cells are located in the crossings. More specifically, the LCD panel includes pixel electrodes and common electrodes to apply electric fields to the respective LC cells. The pixel electrodes are connected to the data lines via sources and drains of thin film transistors (TFT) that function as switching elements. The gates of the TFTs are connected to the gate lines.
The LCD panel is configured such that a plurality of gate lines and a plurality of data lines cross. The areas formed where the gate lines and the data lines cross define pixel areas. Also, the LCD panel has pixel electrodes and common electrodes to apply electric fields to the respective pixel areas.
On the other hand, the drive circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially provides scan pulses to the gate lines such that the LC cells of the LCD panel may be sequentially operated a specific number of times per minute.
The data driver provides pixel voltage signals to the respective data lines each time when the scan pulse is provided to one of the gate lines.
Therefore, the LCD device displays images thereon as the light transmission of each LC cell is adjusted by electric fields that are applied to the pixel electrodes and the common electrodes in the LC cells, according to the pixel voltage signals.
The gate driver includes a shift register to sequentially output scan pulses as mentioned above. The data driver includes a shift register for outputting sampling signals to sample digital data. The shift registers may output scan pulses or sampling signals uni-directionally or bi-directionally.
FIG. 1 illustrates a conventional shift register including a plurality of stages.
With reference to FIG. 1, the conventional bi-directional shift register includes n stages, ST1-STn that are connected to first and second clock pulse providing lines, first and second voltage providing lines, a drive voltage providing line and a ground voltage providing line. Here, first voltage Vd1 and second voltage Vd2, which are provided to the first and second voltage providing lines, respectively, have opposite phases to one another according to a scan direction. The first and second clock signals CLK are provided to the first and the second clock pulse providing lines, respectively, while their phases are opposite to one another. The first clock pulse is provided to odd stages, and the second clock pulse is provided to even stages.
When the conventional bi-directional shift register operates in the forward direction, stages, ST1 to STn, are sequentially operated to output the scan pulses in the forward direction according to a first start pulse, at least two clock pulses, a first voltage Vd1 with a high level, and a second voltage Vd2 with a low level that are provided to the first stage and is not shown in FIG. 1. Here, stage ST2 to stage STn are enabled by output signals from previous and next stages, respectively.
On the other hand, when the conventional bi-directional shift register is operated in the reverse direction, stages, STn to ST1, are sequentially operated to output the scan pulses in a reverse direction according to a second start pulse, at least two clock pulses, a first voltage Vd1 with a low level, and a second voltage Vd2 with a high level that are provided to stage STn and is not shown in FIG. 1. Here, stage STn−1 to stage ST1 are enabled by output signals from previous and next stages, respectively.
FIG. 2 illustrates a detailed circuit of stage STi of the plurality of stages in the conventional shift register.
Referring to FIG. 2 along with FIG. 1, the stage STi include: a scan direction controller 10 for providing a first voltage Vd1 or a second voltage Vd2 to a scan direction control node QS according to first and second enable signals VOi−1 and VOi+1 to control forward or reverse direction output of a scan pulse; a first node controller 20 for controlling a first node Q1 according to a voltage of the scan direction control node QS; a second node controller 30 for controlling a second node Q2 according to a voltage of the scan direction control node QS and a voltage of the first node Q1; an output unit 50 for outputting input clock signals CLK as scan pulses according to voltages of the first and second nodes Q1 and Q2; a controller 40 of a third node Q3 for providing the first voltage Vd1 or the second voltage Vd2 to the third node Q3 according to the first and second enable signals VOi−1 and VOi+1; and a discharge circuit unit 60 for discharging the voltage of the first node Q1 according to the voltages of the second node Q2 and the third node Q3.
The scan direction controller 10 includes: a 1st transistor T1 that is electrically connected between a first drive voltage input line to which the first voltage Vd1 is input, and to the scan direction control node QS; and a 2nd transistor T2 that is electrically connected between a second drive voltage input line to which the second voltage Vd2 is input, and the scan direction control node QS. Here, the 1st transistor T1 is controlled by the first enable signal VOi−1 that is an output signal output from the stage STi−1, and the 2nd transistor T2 is controlled by the second enable signal VOi+1 that is an output signal output from stage STi+1.
The first node controller 20 includes a 3rd transistor T3 that is electrically connected between a drive voltage input line to which a drive voltage Vdd is input, and the first node Q1. The 3rd transistor T3 is controlled by the voltage of the scan direction control node QS.
The second node controller 30 includes: a 4th transistor T4 forming a diode circuit that is connected to the drive voltage input line, in which the 4th transistor T4 is controlled by the drive voltage Vdd; a 5th transistor T5 connected between the drive voltage input line and the second node Q2, in which the 5th transistor T5 is controlled by the drive voltage Vdd via the 4th transistor T4; a 6th transistor T6 connected between the drive voltage input line via 4th transistor T4 and the ground voltage input line to which the ground voltage Vss is provided, in which the 6th transistor T6 is controlled by the voltage of the first node Q1; a 7th transistor T7 connected between the second node Q2 and the ground voltage input line, in which the 7th transistor T7 is controlled by the voltage of the first node Q1; and an 8th transistor T8 connected between the ground voltage input line and the second node Q2, in which the 8th transistor T8 is controlled by the voltage of the scan direction control node QS.
The discharge circuit unit 60 includes: a 9th transistor T9 connected between the ground voltage input line and the first node Q1, in which the 9th transistor T9 is controlled by voltage of the third node Q3; and a 10th transistor T10 connected between the ground voltage input line and the first node Q1, in which the 10th transistor T10 is controlled by a voltage of the second node Q2.
The third node controller 40 includes: a 12th transistor T12 connected between the first voltage input line to which the first voltage Vd1 is provided, and the third node Q3; and a 13th transistor T13 connected between the second voltage input line to which the second voltage Vd2 is provided, and the third node Q3. Here, the 12th transistor T12 is controlled by the second enable signal VOi+1, and the 13th transistor T13 is controlled by the first enable signal VOi−1.
The out unit 50 includes: a 14th transistor T14 connected between the clock signal CLK1 input line and an output lead; and a 15th transistor T15 connected between the ground voltage input line and the output lead. Here, the 14th and 15th transistors are controlled by the voltages of the first node Q1 and the second node Q2, respectively.
On the other hand, the scan direction controller 10 may be configured to further include an 11th transistor T11 which is connected between the scan direction control node QS and the ground voltage input line, in which the 11th transistor T11 is controlled by the scan pulse output from the output unit 50.
FIG. 3 illustrates waveforms when the circuit of FIG. 2 is operated in the forward direction.
Referring to FIG. 3 along with FIG. 2, operation in the forward direction of the conventional bi-directional shift register will be described in detail as follows:
First, regarding the forward direction scan, the high first voltage Vd1 is provided to the first voltage input line, and the low second voltage Vd2 is provide to the second voltage input line, respectively.
During the interval t1, stage STi receives an first enable signal VOi−1 with a high level from stage STi−1, and a second enable signal VOi+1 with a low level from stage STi+1. Also, during the interval t1, a clock signal CLK with a low level is provided to the clock signal input line.
During the interval t1, the 1st transistor T1 of the scan direction controller 10 is turned on by the high first enable signal VOi−1, and the 2nd transistor T2 is turned off by the low second enable signal VOi+1. Therefore, the scan direction controller 10 provides the high first voltage Vd1 to the scan direction control node QS through the 1st transistor T1.
Here, the high first voltage Vd1 that is applied to the scan direction control node QS, turns on the 3rd transistor T3 of the first node controller 20 and the 8th transistor T8 of the second node controller 30, simultaneously.
The drive voltage Vdd is provided to the first node Q1 via the turned-on 3rd transistor T3. The 6th and 7th transistors T6 and T7 in the second node controller 30 are turned on by the drive voltage Vdd of the first node Q1. Also, as the drive voltage Vdd of the drive voltage input line is provided to the gate of the 5th transistor T5 via the 4th transistor T4, the 5th transistor T5 is turned on, such that the drive voltage Vdd is provided to the second node Q2. Therefore, the ground voltage Vss is provided to the second node Q2 through the 7th and 8th transistors T7 and T8, and, at the same time, the drive voltage Vdd is also provided to the second node Q2 via the 5th transistor T5. However, because the number of transistors providing the ground voltage Vss to the second node Q2 is greater than that of transistors providing the drive voltage Vdd, the second node Q2 is provided with the ground voltage Vss.
Also, during the interval t1, the third node controller 40 is operated such that the 13th transistor T13 is turned on by the high first enable signal VOi−1 to provide the low second voltage Vd2 to the third node Q3, thereby turning off the 9th transistor T9 of the discharge circuit 60. On the other hand, the 10th transistor T10 of the discharge circuit 60 is turned off by the ground voltage Vss of the second node Q2.
In addition, the 14th transistor T14 of the output unit 50 maintains its turned-on state by the drive voltage Vdd of the first node Q1, and the 15th transistor T15 of the output unit 50 also maintains its turned-off state by the ground voltage Vss of the second node Q2. Therefore, the output unit 50 outputs the clock signal CLK1 with a low level that is provided to the clock signal input line to the output lead through the 14th transistor T14. On the other hand, the clock signal CLK1 with a low level that is output from the output unit 50 is provided to a next stage as a first enable signal VOi−1.
During the interval t2, as the first enable signal VOi−1 is in a low level state, and the clock signal CLK1 is in a high level state, the 1st transistor T1 and the 3rd transistor T3 are turned off. Also, the 14th transistor of the output unit 50 is turned on. Namely, since the first node Q1 is floated as the 1st transistor T1 and the 3rd transistor T3 are turned off, it is bootstrapped by parasitic capacitor Cgs (not shown) between the gate and source of the 14th transistor T14 of the output unit 50, according to the high clock signal. Therefore, its voltage is greater than the drive voltage Vdd, and thus the 14th transistor T14 of the output unit 50 is firmly turned on. As the 14th transistor T14 is turned on, the high clock signal CLK is quickly provided to the output lead through the 14th transistor T14. Therefore, stage STi can output an output signal VOi with a high level.
On the other hand, during the interval t2, the stage STi+1 is operated like during the interval t1 of stage STi. Namely, stage STi+1 provides the drive voltage Vdd to the first node Q1 in response to the first enable signal VOi−1 to be input to the stage STi+1, which corresponds to the high output signal VOi, which is output from the stage STi.
After that, during the interval t3, the first enable signal VOi−1 maintains its low level, and the clock signal is in a low level state. Therefore, the 1st transistor T1 and the 3rd transistor T3 are turned off.
On the other hand, during the interval t3, as the high second enable signal VOi+1 is provided to the 12th transistor T12 of the third node controller 40 from the stage STi+1, the third node Q3 is charged with the first voltage Vd1 such that its level is high. Therefore, the 9th transistor T9 of the discharge circuit unit 60 is turned on by the first voltage Vd1 of the third node Q3, such that the ground voltage Vss can be provided to the first node Q1.
Because the ground voltage Vss is provided to the first node Q1 through the 9th transistor T9 of the discharge circuit unit 60, the first node Q1 is in a low level state. The 14th transistor T14 of the output unit 50 is turned off by the ground voltage Vss provided to the first node Q1. The drive voltage Vdd is provided to the second node Q2 through the 5th transistor T5. Here, as the 6th and 7th transistors T6 and T7 are turned off by the ground voltage Vss of the first node Q1, the 5th transistor T5 is turned on by the drive voltage Vdd provided through the 4th transistor T4. Therefore, the output unit 50 outputs the ground voltage Vss, or an output signal VOi with a low level, to the output lead through the 15th transistor T15.
After that, during the interval t4, as the second enable signal VOi+1 is in a low level state, and the 12th transistor T12 is turned off, the third node Q3 is floated and maintains its high level.
FIG. 4 illustrates waveforms when the circuit of FIG. 2 is operated in the reverse direction.
Referring to FIG. 4 along with FIG. 2, reverse operations of the conventional bi-directional shift register will be described in detail as follows:
Regarding the reverse direction scan, the low first voltage Vd1 is provided to the first voltage input line, and the high second voltage Vd2 is provided to the second voltage input line, respectively.
During the interval t1, stage STi receives the first enable signal VOi−1 with a low level from stage STi−1, and the second enable signal VOi+1 with a high level from stage STi+1. Also, during the interval t1, a first clock signal CLK1 with a low level is provided to the clock signal input line.
During the interval t1, the 2nd transistor T2 of the scan direction control unit 10 is turned on by the high second enable signal VOi+1, or an output signal of stage STi+1, and the 1st transistor T1 of the scan direction controller 10 is turned off by the first enable signal VOi−1 with a low level that is output from the stage STi−1. Therefore, the scan direction controller 10 provides the high second voltage Vd2 that is provided to the second voltage input line to the scan direction control node QS through the 2nd transistor T2.
Here, the high second voltage Vd2, which is applied to the scan direction control node QS, turns on the 3rd transistor T3 of the first node controller 20 and the 8th transistor T8 of the second node controller 30, simultaneously.
The drive voltage Vdd is provided to the first node Q1 via the turned-on 3rd transistor T3. The 6th and 7th transistors T6 and T7 in the second node controller 30 are turned on by the drive voltage Vdd of the first node Q1.
Also, as the drive voltage Vdd of the drive voltage input line is provided to the gate of the 5th transistor T5 via the 4th transistor T4 and the 5th transistor T5 is turned on, such that the drive voltage Vdd is provided to the second node Q2. Therefore, the ground voltage Vss is provided to the second node Q2 through the 7th and 8th transistors T7 and T8, and, at the same time, the drive voltage Vdd is also provided to the second node Q2 via the 5th transistor T5. However, because the number of transistors providing the ground voltage Vss to the second node Q2 is greater than the number of transistors providing the drive voltage Vdd, the second node Q2 is provided with the ground voltage Vss.
Also, during the interval t1, the third node controller 40 operates such that the 12th transistor T12 is turned on by the high second enable signal VOi+1 to provide the low first voltage Vd1 to the third node Q3, thereby turning off the 9th transistor T9 of the first discharge circuit 60. On the other hand, the 10th transistor T10 of the first discharge circuit 60 is turned off by the ground voltage Vss of the second node Q2.
In addition, the 14th transistor T14 of the output unit 50 maintains its turned-on state due to the drive voltage Vdd of the first node Q1, and the 15th transistor T15 of the output unit 50 also maintains its turned-off state due to the ground voltage Vss of the second node Q2. Therefore, the output unit 50 outputs the clock signal CLK1 with a low level, which is provided to the clock signal input line, to the output lead through the 14th transistor T14. On the other hand, the clock signal CLK1 with a low level, which is output from the output unit 50, is provided to the previous stage as a first enable signal VOi−1.
During the interval t2, as the second enable signal VOi+1 has a low level state and the clock signal CLK1 has a high level state, the 2nd transistor T2 and the 3rd transistor T3 are turned off. Also, the 14th transistor of the output unit 50 is turned on. Namely, because the first node Q1 is floated as the 2nd transistor T2 and the 3rd transistor T3 are turned off, it is bootstrapped by parasitic capacitor Cgs between the gate and source of the 14th transistor T14 of the output unit 14, according to the high clock signal. Therefore, its voltage is greater than the drive voltage Vdd, and thus the 14th transistor T14 of the output unit 50 is turned on. As the 14th transistor T14 is turned on, the high clock signal CLK is quickly provided to the output lead through the 14th transistor T14. Therefore, stage STi outputs an output signal VOi with a high level.
On the other hand, during the interval t2, the first node Q1 of stage STi−1 provided with the drive voltage Vdd in response to the second enable signal VOi+1 to the stage STi−1, which corresponds to the output signal VOi with a high level that is output from the stage STi.
After that, during the interval t3, the second enable signal VOi+1 maintains its low level, and the clock signal CLK is in a low level state. Therefore, the 2nd transistor T2 and the 3rd transistor T3 are turned off.
On the other hand, during the interval t3, the first enable signal VOi−1 has a high level. As the high first enable signal VOi−1 is provided to the 13th transistor T13 of the third node controller 40 from the stage STi−1, the third node Q3 is charged with the second voltage Vd2 such that its level is high. Therefore, the 9th transistor T9 of the discharge circuit unit 60 is turned on by the second voltage Vd2 of the third node Q3, such that the ground voltage Vss is provided to the first node Q1.
Because the ground voltage Vss is provided to the first node Q1 through the 9th transistor T9 of the discharge circuit unit 60, the first node Q1 is in a low level state. The 14th transistor T14 of the output unit 50 is turned off by the ground voltage Vss provided to the first node Q1 because the first node Q1 maintains its discharge state. On the other hand, as the 6th and 7th transistors T6 and T7 are turned off by the ground voltage Vss of the first node Q1, the 5th transistor T5 is turned on by the drive voltage Vdd provided to the 4th transistor T4, the drive voltage Vdd is provided to the second node Q2 through the 5th transistor T5. Therefore, the output unit 50 outputs the ground voltage Vss, or an output signal VOi with a low level, to the output lead through the 15th transistor T15.
After that, during the interval t4, the first enable signal VOi−1 is in a low level state, and the 12th transistor T12 is turned off. But, the third node Q3 is floated and maintains its high level.
Although the conventional bi-direction shift register is operated such that the 9th transistor can input a successive high voltage to its gate as the voltage of the third node Q3 is maintained at a low level during the intervals t1 and t2 and kept at a high state during the other intervals, it has disadvantages in that the 9th transistor suffers from aging due to bias stress caused by a voltage with a high level applied to the gate, in which the high voltage is provided to the third node Q3.